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<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
</li>
</ul>
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<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>D:\Gowin\Gowin_V1.9.8\IDE\ipcore\VFB\data\vfb_top.v<br>
D:\Gowin\Gowin_V1.9.8\IDE\ipcore\VFB\data\vfb_wrapper.vp<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">GowinSynthesis Version</td>
<td>GowinSynthesis V1.9.8</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV55PG484C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-55</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Thu Oct 21 12:54:51 2021
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>Video_Frame_Buffer_Top_32</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 32.883MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 32.883MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.056s, Peak memory usage = 32.883MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 32.883MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.078s, Peak memory usage = 32.883MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 32.883MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 32.883MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 32.883MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 32.883MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.062s, Peak memory usage = 32.883MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 32.883MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 32.883MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 47.707MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.133s, Peak memory usage = 47.707MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.084s, Peak memory usage = 47.707MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 47.707MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>378</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>377</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>174</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>203</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>365</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFF</td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFS</td>
<td>8</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFR</td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFP</td>
<td>16</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFPE</td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFC</td>
<td>217</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFCE</td>
<td>110</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFNP</td>
<td>8</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>667</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>211</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>220</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>236</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>82</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>82</td>
</tr>
<tr>
<td class="label"><b>SSRAM </b></td>
<td>6</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspRAM16S4</td>
<td>6</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>4</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>4</td>
</tr>
<tr>
<td class="label"><b>BSRAM </b></td>
<td>8</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSDPB</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSDPX9B</td>
<td>7</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>789(671 LUTs, 82 ALUs, 6 SSRAMs) / 54720</td>
<td>1%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>365 / 41997</td>
<td>1%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 41997</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>365 / 41997</td>
<td>1%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>8 / 140</td>
<td>6%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>I_vin0_clk</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>I_vin0_clk_ibuf/I </td>
</tr>
<tr>
<td>I_dma_clk</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>I_dma_clk_ibuf/I </td>
</tr>
<tr>
<td>I_vout0_clk</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>I_vout0_clk_ibuf/I </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>No.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>I_vin0_clk</td>
<td>100.0(MHz)</td>
<td>176.6(MHz)</td>
<td>9</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>I_dma_clk</td>
<td>100.0(MHz)</td>
<td>153.8(MHz)</td>
<td>10</td>
<td>TOP</td>
</tr>
<tr>
<td>3</td>
<td>I_vout0_clk</td>
<td>100.0(MHz)</td>
<td>192.6(MHz)</td>
<td>9</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.498</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.330</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Full_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_dma_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>I_dma_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_dma_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_dma_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>217</td>
<td>I_dma_clk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s1/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s1/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s2/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>132</td>
<td>vfb_ddr3_wrapper_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s2/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n64_s2/I2</td>
</tr>
<tr>
<td>2.577</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n64_s2/F</td>
</tr>
<tr>
<td>2.814</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_0_s/I1</td>
</tr>
<tr>
<td>3.384</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_0_s/COUT</td>
</tr>
<tr>
<td>3.384</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_1_s/CIN</td>
</tr>
<tr>
<td>3.419</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_1_s/COUT</td>
</tr>
<tr>
<td>3.419</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s/CIN</td>
</tr>
<tr>
<td>3.454</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s/COUT</td>
</tr>
<tr>
<td>3.454</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_3_s/CIN</td>
</tr>
<tr>
<td>3.489</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_3_s/COUT</td>
</tr>
<tr>
<td>3.489</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_4_s/CIN</td>
</tr>
<tr>
<td>3.524</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_4_s/COUT</td>
</tr>
<tr>
<td>3.524</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_5_s/CIN</td>
</tr>
<tr>
<td>3.560</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_5_s/COUT</td>
</tr>
<tr>
<td>3.560</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_6_s/CIN</td>
</tr>
<tr>
<td>3.595</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_6_s/COUT</td>
</tr>
<tr>
<td>3.595</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_7_s/CIN</td>
</tr>
<tr>
<td>4.065</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_7_s/SUM</td>
</tr>
<tr>
<td>4.302</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wgraynext_6_s0/I1</td>
</tr>
<tr>
<td>4.857</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wgraynext_6_s0/F</td>
</tr>
<tr>
<td>5.094</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s6/I0</td>
</tr>
<tr>
<td>5.611</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s6/F</td>
</tr>
<tr>
<td>5.848</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s3/I1</td>
</tr>
<tr>
<td>6.403</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s3/F</td>
</tr>
<tr>
<td>6.640</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s0/I2</td>
</tr>
<tr>
<td>7.093</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>7.330</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Full_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_dma_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_dma_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>217</td>
<td>I_dma_clk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Full_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Full_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>10</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 4.339, 67.096%; route: 1.896, 29.317%; tC2Q: 0.232, 3.587%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.117</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.710</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>vfb_ddr3_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_dma_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>I_dma_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_dma_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_dma_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>217</td>
<td>I_dma_clk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>16</td>
<td>vfb_ddr3_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma0_wr_data_end_s/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>23</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma0_wr_data_end_s/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n678_s0/I1</td>
</tr>
<tr>
<td>2.679</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n678_s0/F</td>
</tr>
<tr>
<td>2.916</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_0_s/I1</td>
</tr>
<tr>
<td>3.486</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_0_s/COUT</td>
</tr>
<tr>
<td>3.486</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_1_s/CIN</td>
</tr>
<tr>
<td>3.521</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_1_s/COUT</td>
</tr>
<tr>
<td>3.521</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s/CIN</td>
</tr>
<tr>
<td>3.556</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s/COUT</td>
</tr>
<tr>
<td>3.556</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_3_s/CIN</td>
</tr>
<tr>
<td>3.591</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_3_s/COUT</td>
</tr>
<tr>
<td>3.591</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_4_s/CIN</td>
</tr>
<tr>
<td>3.626</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_4_s/COUT</td>
</tr>
<tr>
<td>3.626</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s/CIN</td>
</tr>
<tr>
<td>3.662</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s/COUT</td>
</tr>
<tr>
<td>3.662</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_6_s/CIN</td>
</tr>
<tr>
<td>3.697</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_6_s/COUT</td>
</tr>
<tr>
<td>3.697</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_7_s/CIN</td>
</tr>
<tr>
<td>3.732</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_7_s/COUT</td>
</tr>
<tr>
<td>3.732</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_8_s/CIN</td>
</tr>
<tr>
<td>3.767</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_8_s/COUT</td>
</tr>
<tr>
<td>3.767</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_9_s/CIN</td>
</tr>
<tr>
<td>4.237</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_9_s/SUM</td>
</tr>
<tr>
<td>4.474</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rgraynext_8_s0/I1</td>
</tr>
<tr>
<td>5.029</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rgraynext_8_s0/F</td>
</tr>
<tr>
<td>5.266</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n708_s0/I0</td>
</tr>
<tr>
<td>5.783</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n708_s0/COUT</td>
</tr>
<tr>
<td>6.020</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/I2</td>
</tr>
<tr>
<td>6.473</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/F</td>
</tr>
<tr>
<td>6.710</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_dma_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_dma_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>217</td>
<td>I_dma_clk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>9</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 3.957, 67.662%; route: 1.659, 28.371%; tC2Q: 0.232, 3.967%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.337</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.491</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Full_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_vin0_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>I_vin0_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_vin0_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_vin0_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>83</td>
<td>I_vin0_clk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n56_s1/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n56_s1/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_0_s/I1</td>
</tr>
<tr>
<td>2.694</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_0_s/COUT</td>
</tr>
<tr>
<td>2.694</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_1_s/CIN</td>
</tr>
<tr>
<td>2.729</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_1_s/COUT</td>
</tr>
<tr>
<td>2.729</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_2_s/CIN</td>
</tr>
<tr>
<td>2.764</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_2_s/COUT</td>
</tr>
<tr>
<td>2.764</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_3_s/CIN</td>
</tr>
<tr>
<td>2.799</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_3_s/COUT</td>
</tr>
<tr>
<td>2.799</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_4_s/CIN</td>
</tr>
<tr>
<td>2.834</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_4_s/COUT</td>
</tr>
<tr>
<td>2.834</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_5_s/CIN</td>
</tr>
<tr>
<td>2.870</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_5_s/COUT</td>
</tr>
<tr>
<td>2.870</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_6_s/CIN</td>
</tr>
<tr>
<td>2.905</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_6_s/COUT</td>
</tr>
<tr>
<td>2.905</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_7_s/CIN</td>
</tr>
<tr>
<td>2.940</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_7_s/COUT</td>
</tr>
<tr>
<td>2.940</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_8_s/CIN</td>
</tr>
<tr>
<td>3.410</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_8_s/SUM</td>
</tr>
<tr>
<td>3.647</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wgraynext_5_s0/I1</td>
</tr>
<tr>
<td>4.202</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wgraynext_5_s0/F</td>
</tr>
<tr>
<td>4.439</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/wfull_val_s5/I0</td>
</tr>
<tr>
<td>4.956</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/wfull_val_s5/F</td>
</tr>
<tr>
<td>5.193</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/wfull_val_s4/I2</td>
</tr>
<tr>
<td>5.646</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/wfull_val_s4/F</td>
</tr>
<tr>
<td>5.883</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/wfull_val_s0/I3</td>
</tr>
<tr>
<td>6.254</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>6.491</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Full_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_vin0_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_vin0_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>83</td>
<td>I_vin0_clk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Full_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Full_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>9</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 3.737, 66.402%; route: 1.659, 29.476%; tC2Q: 0.232, 4.122%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.807</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.021</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_de_32b_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_vout0_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>I_vout0_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_vout0_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_vout0_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>87</td>
<td>I_vout0_clk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_de_32b_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_de_32b_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n68_s0/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n68_s0/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_0_s/I1</td>
</tr>
<tr>
<td>2.694</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_0_s/COUT</td>
</tr>
<tr>
<td>2.694</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_1_s/CIN</td>
</tr>
<tr>
<td>2.729</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_1_s/COUT</td>
</tr>
<tr>
<td>2.729</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_2_s/CIN</td>
</tr>
<tr>
<td>2.764</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_2_s/COUT</td>
</tr>
<tr>
<td>2.764</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_3_s/CIN</td>
</tr>
<tr>
<td>2.799</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_3_s/COUT</td>
</tr>
<tr>
<td>2.799</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_4_s/CIN</td>
</tr>
<tr>
<td>2.834</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_4_s/COUT</td>
</tr>
<tr>
<td>2.834</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_5_s/CIN</td>
</tr>
<tr>
<td>2.870</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_5_s/COUT</td>
</tr>
<tr>
<td>2.870</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_6_s/CIN</td>
</tr>
<tr>
<td>2.905</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_6_s/COUT</td>
</tr>
<tr>
<td>2.905</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_7_s/CIN</td>
</tr>
<tr>
<td>2.940</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_7_s/COUT</td>
</tr>
<tr>
<td>2.940</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_8_s/CIN</td>
</tr>
<tr>
<td>2.975</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_8_s/COUT</td>
</tr>
<tr>
<td>2.975</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_9_s/CIN</td>
</tr>
<tr>
<td>3.010</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_9_s/COUT</td>
</tr>
<tr>
<td>3.010</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_10_s/CIN</td>
</tr>
<tr>
<td>3.480</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_10_s/SUM</td>
</tr>
<tr>
<td>3.717</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_7_s0/I1</td>
</tr>
<tr>
<td>4.272</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_7_s0/F</td>
</tr>
<tr>
<td>4.509</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n653_s0/I0</td>
</tr>
<tr>
<td>5.058</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n653_s0/COUT</td>
</tr>
<tr>
<td>5.058</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n654_s0/CIN</td>
</tr>
<tr>
<td>5.094</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n654_s0/COUT</td>
</tr>
<tr>
<td>5.331</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rempty_val_s1/I2</td>
</tr>
<tr>
<td>5.784</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rempty_val_s1/F</td>
</tr>
<tr>
<td>6.021</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_vout0_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_vout0_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>87</td>
<td>I_vout0_clk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>9</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 3.504, 67.933%; route: 1.422, 27.569%; tC2Q: 0.232, 4.498%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.904</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.923</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_dma_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>I_dma_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_dma_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_dma_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>217</td>
<td>I_dma_clk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s2/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>8</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s2/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s8/AD[0](chk_dup)</td>
</tr>
<tr>
<td>1.849</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s8/DO[3]</td>
</tr>
<tr>
<td>2.086</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_3_s2/I1</td>
</tr>
<tr>
<td>2.641</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_3_s2/F</td>
</tr>
<tr>
<td>2.878</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_3_s3/I0</td>
</tr>
<tr>
<td>3.395</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_3_s3/F</td>
</tr>
<tr>
<td>3.632</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s0/I0</td>
</tr>
<tr>
<td>4.148</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s0/F</td>
</tr>
<tr>
<td>4.385</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/I0</td>
</tr>
<tr>
<td>4.934</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/COUT</td>
</tr>
<tr>
<td>4.934</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/CIN</td>
</tr>
<tr>
<td>4.970</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/COUT</td>
</tr>
<tr>
<td>4.970</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/CIN</td>
</tr>
<tr>
<td>5.005</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/COUT</td>
</tr>
<tr>
<td>5.005</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/CIN</td>
</tr>
<tr>
<td>5.040</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/COUT</td>
</tr>
<tr>
<td>5.040</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/CIN</td>
</tr>
<tr>
<td>5.075</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/COUT</td>
</tr>
<tr>
<td>5.075</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/CIN</td>
</tr>
<tr>
<td>5.111</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/COUT</td>
</tr>
<tr>
<td>5.111</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/CIN</td>
</tr>
<tr>
<td>5.146</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/COUT</td>
</tr>
<tr>
<td>5.146</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_7_s/CIN</td>
</tr>
<tr>
<td>5.181</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_7_s/COUT</td>
</tr>
<tr>
<td>5.181</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_8_s/CIN</td>
</tr>
<tr>
<td>5.216</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_8_s/COUT</td>
</tr>
<tr>
<td>5.216</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_9_s/CIN</td>
</tr>
<tr>
<td>5.686</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_9_s/SUM</td>
</tr>
<tr>
<td>5.923</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_9_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_dma_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_dma_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>217</td>
<td>I_dma_clk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_9_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_9_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 3.407, 67.317%; route: 1.422, 28.099%; tC2Q: 0.232, 4.584%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
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